july 2015 fcd5n60_f085 n-channel superfet ? mosfet ?2015 fairchild semiconductor corporation fcd5n60_f085 rev. 1.0 www.fairchildsemi.com 1 fcd5n60_f085 n-channel superfet ? mosfet 600 v, 4.6 a, 1.1 features ? 600v, 4.6a, typ. r ds(on) =860m ? @v gs =10v ? ultra low gate charge (typ. q g = 16 nc) ? uis capability ? rohs compliant ? qualified to aec q101 applications ? automotive on board charger ? automotive dc/dc converter for hev description superfettm is fairchild?s proprietary new generation of high voltage mosfets utilizing an advanced charge balance mechanism for outstanding low on-resistance and lower gate charge performance. this advanced technology has been tailored to minimize con duction loss, provide superior switching performance, and withstand extreme dv/dt rate and higher avalanche energy. consequently, superfet is suitable for various automotive dc/dc p ower conversion. d g s g s d to-252 d-pak (to-252) mosfet maximum ratings t j = 25c unless otherwise noted. symbol parameter ratings units v dss drain-to-source voltage 600 v v gs gate-to-source voltage 30 v i d drain current - continuous (v gs =10) (note 1) t c = 25c 4.6 a pulsed drain current t c = 25c see figure 4 e as single pulse avalanche energy (note 1) 29 mj p d power dissipation 54 w derate above 25 o c1 . 5 6 w / o c t j , t stg operating and storage temperature -55 to + 150 o c r jc thermal resistance, junction to case 2.3 o c/w r ja maximum thermal resistance, junction to ambient (note 2) 83 o c/w package marking and ordering information device marking device package reel size tape width quantity fcd5n60 fcd5n60_f085 d-pak(to-252) 13? 16mm 2500units notes: 1: starting t j = 25c, l = 10 m h, i as = 2.4a, v dd = 100v during inductor charging and v dd = 0v during time in avalanche. 2: r ja is the sum of the junction-to-case and case-to-ambient thermal resistance, where the case thermal reference is defined as the solder mounting surface of the drain pins. r jc is guaranteed by design, while r ja is determined by the board design. the maximum rating presented here is based on mounting on a 1 in 2 pad of 2oz copper. for ? current ? package ? drawing, ? please ? refer ? to ? the ? fairchild ? web \ site ? at ? http://www.fairchildsemi.com/package \ drawings/to/ to252a03.pdf.
fcd5n60_f085 n-channel superfet ? mosfet ?2015 fairchild semiconductor corporation fcd5n60_f085 rev. 1.0 www.fairchildsemi.com 2 electrical characteristics t j = 25c unless otherwise noted. off characteristics on characteristics dynamic characteristics symbol parameter test conditions min. typ. max. units b vdss drain-to-source breakdown voltage i d = 250 p a, v gs = 0v 600 - - v i dss drain-to-source leakage current v ds = 600v, t j = 25 o c --1 p a v gs = 0v t j = 150 o c (note 4) - - 10 p a i gss gate-to-source leakage current v gs = 30v - - 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 p a 3.0 - 5.0 v r ds(on) drain to source on resistance i d = 4.6a, v gs = 10v t j = 25 o c -0.861.1 : t j = 150 o c (note 4) - 2.5 3.2 : c iss input capacitance v ds = 25v, v gs = 0v, f = 1mhz - 570 - pf c oss output capacitance - 280 - pf c rss reverse transfer capacitance - 20 - pf r g gate resistance f = 1mhz - 1.9 - : q g(tot) total gate charge v gs = 0 to 10v v dd = 480v i d = 4.6a -1621nc q g(th) threshold gate charge v gs = 0 to 2v - 1.0 - nc q gs gate-to-source gate charge -3.2-nc q gd gate-to-drain ?miller? charge - 7.6 - nc switching characteristics drain-source diode characteristics note: 4: the maximum value is specified by design at t j = 150c. product is not tested to this condition in production. t on turn-on time v dd = 300v, i d = 4.6a, v gs = 10v, r gen = 25 : - - 84 ns t d(on) turn-on delay - 18 - ns t r rise time - 19 - ns t d(off) turn-off delay - 48 - ns t f fall time - 13 - ns t off turn-off time - - 178 ns v sd source-to-drain diode voltage i sd = 4.6a, v gs = 0v - - 1.25 v t rr reverse-recovery time v dd = 480v, i f = 4.6a, di sd /dt = 100a/ p s - 190 250 ns q rr reverse-recovery charge - 1.7 2.2 p c
fcd5n60_f085 n-channel superfet ? mosfet ?2015 fairchild semiconductor corporation fcd5n60_f085 rev. 1.0 www.fairchildsemi.com 3 typical characteristics figure 1. normalized power dissipation vs. case temperature 0 255075100125150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 power dissipation multiplier t c , case temperature( o c) figure 2. maximum continuous drain current vs. case temperature 25 50 75 100 125 150 175 0 2 4 6 8 current limited by package v gs = 10v i d , drain current (a) t c , case temperature( o c) figure 3. 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 0.01 0.1 1 single pulse d = 0.50 0.20 0.10 0.05 0.02 0.01 normalized thermal impedance, z jc t, rectangular pulse duration(s) duty cycle - descending order 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z ja x r ja + t c p dm t 1 t 2 normalized maximum transient thermal impedance figure 4. peak current capability 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 1 10 100 v gs = 10v single pulse i dm , peak current (a) t, rectangular pulse duration(s) t c = 25 o c i = i 2 150 - t c 125 for temperatures above 25 o c derate peak current as follows:
fcd5n60_f085 n-channel superfet ? mosfet ?2015 fairchild semiconductor corporation fcd5n60_f085 rev. 1.0 www.fairchildsemi.com 4 figure 5. 1 10 100 1000 0.01 0.1 1 10 100 10us 2000 100us 1ms 10ms i d , drain current (a) v ds , drain to source voltage (v) operation in this area may be limited by r ds(on) single pulse t j = max rated t c = 25 o c 100ms forward bias safe operating area figure 6. 0481216 0 2 4 6 8 10 v dd = 240v v dd =300v i d = 4.6a v dd = 360v q g , gate charge(nc) v gs , gate to source voltage(v) gate charge vs. gate to source voltage figure 7. 345678910 0 4 8 12 16 20 t j = -55 o c t j = 25 o c t j = 150 o c pulse duration = 80 s duty cycle = 0.5% max v dd = 20v i d , drain current (a) v gs , gate to source voltage (v) transfer characteristics figure 8. 0.2 0.4 0.6 0.8 1.0 1.2 0.1 1 10 20 t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) forward diode characteristics figure 9. 0 4 8 12 16 20 0 2 4 6 8 10 12 14 v gs 15v top 10v 8v 7v 6v 5.5v 5v bottom 80 s pulse width tj=25 o c i d , drain current (a) v ds , drain to source voltage (v) saturation characteristics figure 10. 0 4 8 12 16 20 0 1 2 3 4 5 6 7 8 v gs 15v top 10v 8v 7v 6v 5.5v 5v bottom 80 s pulse width tj=150 o c i d , drain current (a) v ds , drain to source voltage (v) saturation characteristics typical characteristics
fcd5n60_f085 n-channel superfet ? mosfet ?2015 fairchild semiconductor corporation fcd5n60_f085 rev. 1.0 www.fairchildsemi.com 5 figure 11. 5678910 0 1 2 3 4 5 6 i d = 4.6a pulse duration = 80 s duty cycle = 0.5% max r ds(on) , drain to source on-resistance ( ) v gs , gate to source voltage (v) t j = 25 o c t j = 150 o c r dson vs. gate voltage figure 12. normalized r dson vs. junction temperature -80 -40 0 40 80 120 160 0.0 0.5 1.0 1.5 2.0 2.5 3.0 pulse duration = 80 s duty cycle = 0.5% max i d = 4.6a v gs = 10v normalized drain to source on-resistance t j , junction temperature ( o c ) figure 13. -80 -40 0 40 80 120 160 0.4 0.6 0.8 1.0 1.2 1.4 v gs = v ds i d = 250 a normalized gate threshold voltage t j , junction temperature( o c) normalized gate threshold voltage vs. temperature figure 14. -80 -40 0 40 80 120 160 0.8 0.9 1.0 1.1 1.2 i d = 1ma normalized drain to source breakdown voltage t j , junction temperature ( o c) normalized drain to source breakdown voltage vs. junction temperature figure 15. 0.1 1 10 100 1000 1 10 100 1000 10000 f = 1mhz v gs = 0v c rss c oss c iss capacitance (pf) v ds , drain to source voltage ( v ) capacitance vs. drain to source voltage figure 16. typical characteristics
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